RE
Design Verification Engineer- Senior Associate- Technology
Referral Publicisgroupe Icims Com
Publiée le
15/07/2026
Contrat
CDD / Temporaire · 1-3 mois
Localisation
Bucharest, UNAVAILABLE, RO; Iasi, UNAVAILABLE, RO; Cluj-Napoca, UNAVAILABLE, RO; Timisoara, UNAVAILABLE, RO; Brasov, UNAVAILABLE, RO
Taille équipe
15-50 emp.
Rémunération
Inconnue
Missions clés
Contribuer au développement de l'infrastructure front-end
Profil recherché
0-1 ans d'expérience · Résolution de problèmes · Créativité · Pensée critique
Outils & compétences
System Verilog, UVM, REST API
Le poste en détail
Company Description
Tremend is the newest global software engineering hub for Publicis Sapient. For over 20 years, the company has been infusing its advanced technical expertise into complex and innovative solutions that meet today's digital transformation needs and pave the way for a better and smarter future. By joining forces with Publicis Sapient we're accelerating the impact, providing a good mix of talented engineers, technology, continuous improvement, innovation, and R&D. Here, you'll have the opportunity to unleash your potential, powering up advanced software solutions for some of the world's most iconic brands. Embrace your passion for technology, creativity, and continuous improvement, and join us in making a difference through engineering.
Job Description
Tremend is looking for a Design Verification Engineer to join our team of bright thinkers and doers. You’ll use your problem-solving creativity to figure out our client's most complex and challenging problems across different industries. We are on a mission to transform the world, and you will be instrumental in shaping how we do it with your ideas, thoughts, and solutions. Responsibilities:
Full front-end chip verification from verification plans to coverage closure
A significant input in developing the next generation of core technology products for our customers
Lead and mentor the young generation of verification engineers on the team
Qualifications:
Good working knowledge of System Verilog and UVM
Experience with interconnects and memory controllers is a plus
Experience with third party VIPs in their verification environment is a plus
SOC level experience is a plus
Working knowledge of regression and coverage analysis tools is required
Has developed an environment and taken a module to verification closure OR has significantly altered an existing environment and taken a module to verification closure
Working experience with modern revision control systems: Git, Perforce, SVN
Working experience with JIRA or similar ticketing systems
Additional Information
Besides an exciting job in a tremendous team, here's what you can expect:
A fast-paced tech environment
Continuous growth & learning
Open feedback culture
Room for own initiative & ideas
Transparency about results & strategy
Recognition & reward for hard work
Working with a flexible schedule
Medical subscription
Meal tickets
Extra vacation days - starting with 25 vacation days
Many others perks.